FIG. 1 is a block diagram showing a conventional video detector circuit. As shown in FIG. 1, the conventional video detector circuit basically consists of a voltage controlled oscillator (VCO) 1, a phase comparator 2, a filter 3, and a bias circuit 4. The phase comparator 2 compares a phase of the output of the V.C.O. 1 with an intermediate frequency (IF) signal input from a tuner (not shown). The filter 3 outputs a low frequency part in the output from the phase comparator 2. The bias circuit 4 applies a direct current bias (DC bias) to the output of the filter 3 in order to determine a free-running state of a Phase Locked Loop (PLL) which consists of the VCO 1, the phase comparator 2, and the filter 3. The VCO is controlled by the output from the filter 3 and the output of the filter 3 is biased by the DC bias from the bias circuit 4.
The detection circuit 5 synchronizes a phase of the video IF signal input from the tuner (not shown) with the phase of the output of the VCO 1, then detects it.
FIG. 2 is a more detailed diagram of the conventional video detector circuit, as shown in FIG. 1.
In FIG. 2, when the video IF signal is input to the phase comparator 2, the phase comparator 2 compares the phase and frequency of the video IF signal Vb input with the VCO frequency and outputs a voltage which is related to the frequency and phase difference between the video IF signal Vb and the VCO output, so that the output from the phase comparator 2 changes, namely increases and decreases, based on an amplitude of the video IF signal Vb input from the tuner (not shown) and the relationship between a phase difference .phi. and a voltage V.sub.A of the output from the filter circuit 3 at a point A. This difference .phi. is the phase difference between the phase of the output Va of the VCO 1 and the phase of the video IF signal Vb. In other words, the amplitude of the video IF signal Vb is changed and the output of the phase comparator 2 is changed irregularly of fluctuated by brightness of pictures to be displayed by a CRT (not shown) because the video IF signal Vb has been amplituded and modulated by a video signal.
For example, as shown in FIG. 3, when the phase difference .phi. between the output Va of the VCO 1 and the video IF signal Vb is 45 degree and the PLL lockes the video IF signal Vb, the amplitude of the video IF signal is fluctuated according to the brightness of the picture.
Specifically, the phase difference between the output of the VCO 1 and the video IF signal is 90.degree. when the frequencies of the output of the VCO 1 and the video IF signal are equal.
In a case that the free-running frequency of the VCO 1 is away from the frequency of the video IF signal input, the relationship between the voltage V.sub.A at point A and the bias voltage in the bias circuit 4 becomes V.sub.A .noteq.V.sub.bias when the VCO 1 is fed by the video IF signal, so that a current I.sub.R (I.sub.R =(V.sub.A -V.sub.bias)/R) flows through the resistance R. The current I.sub.R is provided from the phase comparator 2. This means that the phase difference between the VCO 1 and the video IF signal input is not 90.degree. (degree). In this state, the output of the phase comparator 2 is fluctuated by the amplitude of the video IF signal input, namely by a picture to be displayed on a monitor. The larger there is the difference between the free-running frequency for the VCO 1 and the frequency of the video IF signal, the more the output from the phase comparator 2 is fluctuated by the video IF signal, namely the picture. It causes the change of tile oscillation frequency of the VCO 1, so that audio buzz at a speaker (not shown) is produced and a differential gain (DG) and a differential phase (DP) become poor.
Therefore it must be expected to increase the accuracy of the adjustment of a free-running state in the VCO 1 in order to avoid the problems described above.